Generally, a non-volatile memory comprises a memory cell array. The memory cell array consists of plural memory cells. In addition, each memory cell has a charge storage device, such as floating gate transistor or SONOS transistor, etc.
During a program cycle of a non-volatile memory, a high voltage is received by the memory cell array. Consequently, hot carriers are injected into the floating gate of the floating gate transistor of a selected memory cell. Generally, the high voltage received by the memory cell array is provided by a charge pump circuit.
For example, if no hot carriers are injected into the floating gate, the memory cell has a first storing state (e.g. the state “1”). Whereas, if the hot carriers are injected into the floating gate, the memory cell has a second storing state (e.g. the state “0”).
FIG. 1 is a schematic circuit diagram illustrating the relationship between a charge pump circuit and a memory cell array according to the prior art. An enabling terminal En of the charge pump circuit 110 receives a program enabling signal En-pgm. An output terminal O of the charge pump circuit 110 is connected with a decouple capacitor C and the memory cell array 120. Moreover, a controller (not shown) of the non-volatile memory may issue the program enabling signal En-pgm to determine a program cycle.
When the program enabling signal En-pgm is activated, the program cycle is started. Meanwhile, an output signal Vout with a high voltage (e.g. 15V) is outputted from an output terminal O of the charge pump circuit 110 to the memory cell array 120. The decouple capacitor C may reduce the overshoot voltage and the ripple voltage of the output signal Vout.
Moreover, when the program enabling signal En-pgm is inactivated, the program cycle is ended. Meanwhile, the output signal Vout from the output terminal O of the charge pump circuit 110 is changed to a low voltage (e.g. a ground voltage).
As mentioned above, during the program cycle, the memory cell array 120 receives the high voltage to program the selected memory cell. However, if the output signal Vout is maintained at the high voltage, the programming efficiency of the memory cell array 120 is deteriorated.